STM32F103CBU6TR datasheet(31/96 Pages) STMICROELECTRONICS

31 / 96 page

STM32F103x8, STM32F103xB

Pinouts and pin description

Doc ID 13587 Rev 12

31/96

PB5

I/O

PB5

I2C1_SMBAl

TIM3_CH2 /

SPI1_MOSI

PB6

I/O FT

PB6

I2C1_SCL(8)/

TIM4_CH1(8)

USART1_TX

PB7

I/O FT

PB7

I2C1_SDA(8)/

TIM4_CH2(8)

USART1_RX

BOOT0

PB8

I/O FT

PB8

TIM4_CH3(8)

I2C1_SCL /

CANRX

PB9

I/O FT

PB9

TIM4_CH4(8)

I2C1_SDA/

CANTX

PE0

I/O FT

PE0

TIM4_ETR

PE1

I/O FT

PE1

VSS_3

SVSS_3

100

VDD_3

SVDD_3

I = input, O = output, S = supply.

FT = 5 V tolerant.

Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower

number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1

and USART1 & USART2, respectively. Refer to Table 2 on page 10.

If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should

be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).

PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current

(3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum

load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).

Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even

after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the

Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the

STMicroelectronics website: www.st.com.

Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The VREF+ functionality is provided instead.

This alternate function can be remapped by software to some other port pins (if available on the used package). For more

details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available

from the STMicroelectronics website: www.st.com.

The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages, and C1 and C2 in the

TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be

remapped by software on these pins. For the LQFP100 package, PD0 and PD1 are available by default, so there is no

need for remapping. For more details, refer to the Alternate function I/O and debug configuration section in the

STM32F10xxx reference manual.

The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.

Table 5.

Medium-density STM32F103xx pin definitions (continued)

Pins

Pin name

Main

function(3)

(after reset)

Alternate functions(4)

Default

Remap

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