PCA85232DA datasheet(34/54 Pages) NXP

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PCA85232

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Product data sheet

Rev. 1 — 8 December 2010

34 of 54

NXP Semiconductors

PCA85232

LCD driver for low multiplex rates

11. Dynamic characteristics

[1]

Typical output duty factor: 50 % measured at the CLK output pin.

[2]

For the respective frame frequency ffr see Table 16.

[3]

For the characteristics of VDD at a fixed temperature or of the temperature at a fixed VDD, see Figure 22 and Figure 23.

[4]

For fCLK(ext) > 4 kHz it is recommended to use an external pull-up resistor between pin SYNC and pin VDD. The value of the resistor

should be between 100 k

Ω and 1 MΩ.

[5]

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an

input voltage swing of VSS to VDD.

Table 19.

Dynamic characteristics

VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 1.8 V to 8.0 V; Tamb = −40 °C to +95 °C; unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fclk

clock frequency

on pin CLK;

VDD =5V ± 0.5 V

[1][2][3] 3050 3500 4052 Hz

fclk(ext)

external clock frequency

[4] 700

5000 Hz

tclk(H)

HIGH-level clock time

external clock source used

100

μs

tclk(L)

LOW-level clock time

external clock source used

100

μs

Δf

frame frequency variation

VDD =5V ± 0.5 V

ffr = 146 Hz; Tamb =30 °C

−5.1 -

+5.1

ffr = 135 Hz; Tamb =95 °C

−6.2 -

+6.9

ffr = 157 Hz; Tamb = −40 °C

−7.8 -

+7.6

tPD(SYNC_N) SYNC propagation delay

tSYNC_NL

SYNC LOW time

100

μs

tPD(drv)

driver propagation delay

VLCD = 5 V

μs

Timing characteristics: I2C-bus[5]

fSCL

SCL clock frequency

400

kHz

tBUF

bus free time between a STOP and START

condition

1.3

μs

tHD;STA

hold time (repeated) START condition

0.6

μs

tSU;STA

set-up time for a repeated START condition

0.6

μs

tVD;ACK

data valid acknowledge time

0.9

μs

tLOW

LOW period of the SCL clock

1.3

μs

tHIGH

HIGH period of the SCL clock

0.6

μs

fall time

of both SDA and SCL signals

0.3

μs

rise time

of both SDA and SCL signals

0.3

μs

capacitive load for each bus line

400

tSU;DAT

data set-up time

200

tHD;DAT

data hold time

tSU;STO

set-up time for STOP condition

0.6

μs

tSP

pulse width of spikes that must be

suppressed by the input filter

--50

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