MNSC140CORE datasheet(14/80 Pages) FREESCALE

14 / 80 page

MSC8102 Quad Core Digital Signal Processor, Rev. 12

1-4

Freescale Semiconductor

Signals/Connections

1.4 Direct Slave Interface, System Bus, and Interrupt

Signals

The direct slave interface (DSI) is combined with the system bus because they share some common signal lines.

Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-5

describes the signals in this group.

Note:

Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple

external lines that can connect to these internal signal lines. After reset, the default configuration enables

only IRQ[1–7], but includes two input lines each for IRQ[1–3] and IRQ7. The designer must select one line for

each required interrupt and reconfigure the other external signal line or lines for alternate functions.

Additional alternate IRQ lines and IRQ[8–15] are enabled through the GPIO signal lines.

Table 1-5.

DSI, System Bus, and Interrupt Signals

Signal Name

Type

Description

HD0

SWTE

Input/ Output

Input

Host Data Bus 0

Bit 0 of the DSI data bus.

Software Watchdog Timer Disable.

It is sampled on the rising edge of PORESET signal.

HD1

DSISYNC

Input/ Output

Input

Host Data Bus 1

Bit 1 of the DSI data bus.

DSI Synchronous

Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising

edge of PORESET signal.

HD2

DSI64

Input/ Output

Input

Host Data Bus 2

Bit 2 of the DSI data bus.

DSI 64

Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET signal.

HD3

MODCK1

Input/ Output

Input

Host Data Bus 3

Bit 3 of the DSI data bus.

Clock Mode 1

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD4

MODCK2

Input/ Output

Input

Host Data Bus 4

Bit 4 of the DSI data bus.

Clock Mode 2

Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.

HD5

CNFGS

Input/ Output

Input

Host Data Bus 5

Bit 5 of the DSI data bus.

Configuration Source

One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of PORESET

signal.

HD[6–31]

Input/Output

Host Data Bus 6–31

Bits 6–31 of the DSI data bus.

HD[32–63]

D[32–63]

Input/Output

Host Data Bus 32–63

Bits 32–63 of the DSI data bus.

System Bus Data 32–63

In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives

the valid data on this bus.

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