MNSC140CORE datasheet(15/80 Pages) FREESCALE

15 / 80 page

Direct Slave Interface, System Bus, and Interrupt Signals

MSC8102 Quad Core Digital Signal Processor, Rev. 12

Freescale Semiconductor

1-5

HCID[0–3]

Input

Host Chip ID 0–3

Carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the

Chip_ID, or if HBCS is asserted.

HA[11–29]

Input

Host Bus Address 11–29

Used by external host to access the internal address space.

HWBS[0–3]

HDBS[0–3]

HWBE[0–3]

HDBE[0–3]

Input

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host read or write accesses.

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host write accesses

HWBS[4–7]

HDBS[4–7]

HWBE[4–7]

HDBE[4–7]

PWE[4–7]

PSDDQM[4–7]

PBS[4–7]

Input

Output

Host Write Byte Strobes (In Asynchronous dual mode)

One bit per byte is used as a strobe for host write accesses.

Host Data Byte Strobe (in Asynchronous single mode)

One bit per byte is used as a strobe for host read or write accesses

Host Write Byte Enable (In Synchronous dual mode)

One bit per byte is used to indicate a valid data byte for host write accesses.

Host Data Byte Enable (in Synchronous single mode)

One bit per byte is used as a strobe enable for host read or write accesses

System Bus Write Enable

Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write

operations.

System Bus SDRAM DQM

From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices.

System Bus UPM Byte Select

From the UPM in the memory controller, these signals select specific byte lanes during memory operations.

The timing of these pins is programmed in the UPM. The actual driven value depends on the address and

size of the transaction and the port size of the accessed device.

HRDS

HRW

HRDE

Input

Host Read Data Strobe (In Asynchronous dual mode)

Used as a strobe for host read accesses.

Host Read/Write Select (in Asynchronous/Synchronous single mode)

Host read/write select.

Host Read Data Enable (In Synchronous dual mode)

Indicates valid data for host read accesses.

HBRST

Input

Host Burst

The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous mode

only.

HDST0

Input

Host Data structure 0

Defines the data structure of the host access in DSI little-endian mode.

HDST1

Input

Host Data structure 1

Defines the data structure of the host access in DSI little-endian mode.

HCS

Input

Host Chip Select

DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0–3] matches the Chip_ID.

HBCS

Input

Host Broadcast Chip Select

DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for

broadcast write accesses.

Table 1-5.

DSI, System Bus, and Interrupt Signals (Continued)

Signal Name

Type

Description

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