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PCIMX536AVV8B 데이터시트(PDF) 44 Page - Freescale Semiconductor, Inc

부품명 PCIMX536AVV8B
상세설명  i.MX53xA Automotive and Infotainment Applications Processors
PDF  180 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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PCIMX536AVV8B 데이터시트(HTML) 44 Page - Freescale Semiconductor, Inc

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i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
44
Freescale Semiconductor
Electrical Characteristics
NOTE
CKIL is approximately 32 kHz. TCKIL is one period or approximately 30 μs.
4.6.3
Clock Amplifier Parameters (CKIH1, CKIH2)
The input to Clock Amplifier (CAMP) is internally ac-coupled allowing direct interface to a square wave
or sinusoidal frequency source. No external series capacitors are required.
Table 31 shows the electrical parameters of CAMP.
4.6.4
DPLL Electrical Parameters
Table 32 shows the electrical parameters of digital phase-locked loop (DPLL).
Table 30. WATCHDOG_RST Timing Parameters
ID
Parameter
Min
Max
Unit
CC5
Duration of WATCHDOG_RESET Assertion
1
—
TCKIL
Table 31. CAMP Electrical Parameters (CKIH1, CKIH2)
Parameter
Min
Typ
Max
Unit
Input frequency
8.0
—
40.0
MHz
VIL (for square wave input)
0
—
0.3
V
VIH (for square wave input)1
1 NVCC_CKIH is the supply voltage of CAMP.
NVCC_CKIH – 0.25
—
NVCC_CKIH
V
Sinusoidal input amplitude2
2 Minimum value of the sinusoidal input will be determined during characterization.
0.4
—
VDD
Vp-p
Output duty cycle
45
50
55
%
Table 32. DPLL Electrical Parameters
Parameter
Test Conditions/Remarks
Min
Typ
Max
Unit
Reference clock frequency range1
—10
—
100
MHz
Reference clock frequency range after
pre-divider
—10
—
40
MHz
Output clock frequency range (dpdck_2)
—
300
—
1025
MHz
Pre-division factor2
—1
—
16
—
Multiplication factor integer part
—
5
—
15
—
Multiplication factor numerator3
Should be less than denominator
–67108862
—
67108862
—
Multiplication factor denominator2
—
1
—
67108863
—
Output Duty Cycle
—
48.5
50
51.5
%



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