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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCIMX536AVV8B 데이터시트(PDF) 65 Page - Freescale Semiconductor, Inc |
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PCIMX536AVV8B 데이터시트(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 180 page  Electrical Characteristics i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1 Freescale Semiconductor 65 4.7.2.1 CSPI Master Mode Timing Figure 30 depicts the timing of CSPI in master mode. Table 41 lists the CSPI master mode timing characteristics. Figure 30. CSPI/ECSPI Master Mode Timing Diagram Table 41. CSPI Master Mode Timing Parameters ID Parameter Symbol Min Max Unit CS1 SCLK Cycle Time tclk 60 — ns CS2 SCLK High or Low Time tSW 26 — ns CS3 SCLK Rise or Fall1 1 See specific I/O AC parameters Section 4.5, “I/O AC Parameters” tRISE/FALL —— ns CS4 SSx pulse width tCSLH 26 — ns CS5 SSx Lead Time (Slave Select setup time) tSCS 26 — ns CS6 SSx Lag Time (SS hold time) tHCS 26 — ns CS7 MOSI Propagation Delay (CLOAD =20 pF) tPDmosi –1 21 ns CS8 MISO Setup Time tSmiso 5— ns CS9 MISO Hold Time tHmiso 5— ns CS10 RDY to SSx Time2 2 SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. tSDRY 5— ns CS1 CS7 CS2 CS2 CS4 CS6 CS5 CS8 CS9 SCLK SSx MOSI MISO RDY CS10 CS3 CS3 |
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