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PCIMX536AVV8B 데이터시트(PDF) 75 Page - Freescale Semiconductor, Inc

부품명 PCIMX536AVV8B
상세설명  i.MX53xA Automotive and Infotainment Applications Processors
PDF  180 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PCIMX536AVV8B 데이터시트(HTML) 75 Page - Freescale Semiconductor, Inc

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Electrical Characteristics
i.MX53xA Automotive and Infotainment Applications Processors, Rev. 1
Freescale Semiconductor
75
Figure 36. MII Receive Signal Timing Diagram
4.7.5.2
MII Transmit Signal Timing
The MII transmit signal timing affects the FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER, and
FEC_TX_CLK signals. The transmitter functions correctly up to a FEC_TX_CLK maximum frequency
of 25 MHz + 1%. There is no minimum frequency requirement. In addition, the processor clock frequency
must exceed twice the FEC_TX_CLK frequency.
Table 49 lists MII transmit channel timing parameters. Figure 37 shows MII transmit signal timing
diagram for the values listed in Table 49.
Table 49. MII Transmit Signal Timing
Num
Characteristic1 2
1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode.
2 Test conditions: 25pF on each output signal.
Min
Max
Unit
M5
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER invalid
5
—
ns
M6
FEC_TX_CLK to FEC_TXD[3:0], FEC_TX_EN, FEC_TX_ER valid
—
20
ns
M7
FEC_TX_CLK pulse width high
35%
65%
FEC_TX_CLK period
M8
FEC_TX_CLK pulse width low
35%
65%
FEC_TX_CLK period
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M3
M4
M1
M2



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