MIC3003GFL datasheet(57/74 Pages) MICREL

57 / 74 page

Micrel, Inc.

MIC3003GFL

July 2010

M9999-072910-A

hbwhelp@micrel.com or (408) 955-1690

OEM Configuration Register 2 (OEMCFG2)

D[7]

SMBADR[3]

read/write

D[6]

SMBADR[2]

read/write

D[5]

SMBADR[1]

read/write

D[4]

SMBADR[0]

read/write

D[3]

read/write

D[2]

TRSTCLR[2]

read/write

D[1]

TRSTCLR[1]

read/write

D[0]

TRSTCLR[0]

read/write

Default value

1010 0010b = xxh (device address = 1010 xxxxb)

This value is the basis for using A0 h, A2 h, A4 h, and A6 h as the names of

the different device address spaces of the MIC3003.

Serial address

A6h

Byte address

2 = 02h

Caution: Changes to SMBADR take effect immediately. Any accesses following a write to SMBADR must be to the newly

programmed serial bus address.

A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power

and reset cycles.

Bit(s)

Function

Operation

D[7:4]

SMBADR[3:0]

Most significant four bits of the

serial bus device address

Writes take effect immediately.

D[3:0]

TRSTCLR[2:0]

Set the delay between QGPO and

the clearing of RESETOUT

These three bits set the delay between the de-assertion

edge of the QGPO output in Reset mode and the

subsequent clearing of the three RESETOUT bits in the

RESETOUT Register:

000: Zero delay

001: 17.5 ms typical

010: 22.5 ms typical (default)

011: 27.0 ms typical

100: 45 ms typical

Minimum and maximum values may be found by adding

tolerances of -10% and +10% to the above values.

If Reset mode is not selected, these bits have no function.

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