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IMX53CEC 데이터시트(PDF) 32 Page - Freescale Semiconductor, Inc

부품명 IMX53CEC
상세설명  Applications Processors for Consumer Products
PDF  204 Pages
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제조업체  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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IMX53CEC 데이터시트(HTML) 32 Page - Freescale Semiconductor, Inc

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i.MX53xD Applications Processors for Consumer Products, Rev. 2
32
Freescale Semiconductor
Electrical Characteristics
4.3.2.3
DDR3 Mode I/O DC Parameters
The DDR3 interface fully complies with JESD79-3D DDR3 JEDEC standard release April, 2008. The
parameters in Table 14 are guaranteed per the operating ranges in Table 7, unless otherwise noted.
Differential Input Logic High
Vih(diff)
0.26
See Note2
Differential Input Logic Low
Vil(diff)
See Note2
-0.26
Input current (no pull-up/down)
Iin
Vin = 0 V
Vin=OVDD
—
—
—
—
1
1
μA
Pull-up/Pull-down impedance Mismatch
-15
+15
%
240 Ohm unit calibration resolution
10
Ohm
Keeper Circuit Resistance
—
—
—
1403
—k
Ω
1 Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
2 The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot.
3 Use an off-chip pull resistor of less than 60 k
Ω to override this keeper.
Table 14. DDR3 I/O DC Electrical Parameters
Parameters
Symbol
Test Conditions
Min
Typ
Max
Unit
High-level output voltage
Voh
—
0.8*OVDD1
1 OVDD – I/O power supply (1.425 V–1.575 V for DDR3)
——
V
Low-level output voltage
Vol
—
—
—
0.2*OVDD
V
DC input Logic High
VIH(dc)
—
Vref2+0.1
2 Vref – DDR3 external reference voltage
—OVDD
V
DC input Logic Low
VIL(dc)
—
OVSS
—
Vref-0.1
V
Differential input Logic High
VIH(diff)
—
0.2
—
See Note3
V
Differential input Logic Low
VIL(diff)
—
See Note3
—-0.2
V
Over/undershoot peak
Vpeak
—
—
—
0.4
V
Over/undershoot area
(above OVDD or below OVSS)
Varea
—
—
—
0.67
V x
nS
Termination Voltage
Vtt
Vtt tracking OVDD/2
0.49*OVDD
Vref
0.51*OVDD
V
Input current (no pull-up/down)
Iin
VI = 0 V
VI=OVDD
—
—
—
—
1
1
μA
Pull-up/Pull-down impedance mismatch
—
Minimum impedance
configuration
——
3
Ω
240
Ω unit calibration resolution
—
—
—
—
10
Ω
Keeper Circuit Resistance
—
—
—
1304
—k
Ω
Table 13. LPDDR2 I/O DC Electrical Parameters1 (continued)



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