IMX53CEC datasheet(67/204 Pages) FREESCALE

67 / 204 page

Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

Figure 30 and Table 43 show the data write timing parameters.

Figure 30. DDR SDRAM Data Write Cycle

Figure 31 and Table 44 show the data read timing parameters.

Table 43. DDR SDRAM Write Cycle 1 2 3

1 All timings are refer to Vref level cross point.

Reference load model is 25 ohm resistor from each of the DDR outputs to VDD_REF.

3 To receive the reported setup and hold values, write calibration should be performed in order to locate the DQS in the middle

of DQ window.

Parameter

Symbol

SDCLK = 400 MHz

Unit

Min

Max

DDR17

DQ and DQM setup time to DQS (differential strobe)

tDS

0.285

—

DDR18

DQ and DQM hold time to DQS (differential strobe)

tDH

0.285

—

DDR21

DQS latching rising transitions to associated clock edges

tDQSS

-0.25

+0.25

tCK

DDR22

DQS high level width

tDQSH

0.45

0.55

tCK

DDR23

DQS low level width

tDQSL

0.45

0.55

tCK

SDCLK

SDCLK_B

DQS (output)

DQ (output)

DQM (output)

Data

DDR17

DDR18

DDR21

DDR23

DDR22

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