IMX53CEC datasheet(111/204 Pages) FREESCALE

111 / 204 page

Electrical Characteristics

i.MX53xD Applications Processors for Consumer Products, Rev. 2

Freescale Semiconductor

111

In the timing equations, some timing parameters are used. These parameters depend on the

implementation of the i.MX53xD PATA interface on silicon, the bus buffer used, the cable delay and

cable skew. Table 71 shows ATA timing parameters.

Table 71. PATA Timing Parameters

Name

Description

Value/

Contributing Factor1

1 Values provided where applicable.

Bus clock period (AHB_CLK_ROOT)

Peripheral clock frequency

(7.5 ns for 133 MHz clock)

ti_ds

Set-up time ata_data to ata_iordy edge (UDMA-in only)

UDMA0

UDMA1

UDMA2, UDMA3

UDMA4

UDMA5

15 ns

10 ns

7 ns

5 ns

4 ns

ti_dh

Hold time ata_iordy edge to ata_data (UDMA-in only)

UDMA0, UDMA1, UDMA2, UDMA3, UDMA4

UDMA5

5.0 ns

4.6 ns

tco

Propagation delay bus clock L-to-H to

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data, ata_buffer_en

12.0 ns

tsu

Set-up time ata_data to bus clock L-to-H

8.5 ns

tsui

Set-up time ata_iordy to bus clock H-to-L

8.5 ns

thi

Hold time ata_iordy to bus clock H to L

2.5 ns

tskew1

Max difference in propagation delay bus clock L-to-H to any of following signals

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

7ns

tskew2

Max difference in buffer propagation delay for any of following signals:

ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack,

ata_data (write), ata_buffer_en

Transceiver

tskew3

Max difference in buffer propagation delay for any of following signals ata_iordy,

ata_data (read)

Transceiver

tbuf

Max buffer propagation delay

Transceiver

tcable1

Cable propagation delay for ata_data

Cable

tcable2

Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy,

ata_dmack

Cable

tskew4

Max difference in cable propagation delay between ata_iordy and ata_data (read)

Cable

tskew5

Max difference in cable propagation delay between (ata_dior, ata_diow,

ata_dmack) and ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)

Cable

tskew6

Max difference in cable propagation delay without accounting for ground bounce

Cable

IMX53CEC 데이터시트(PDF) 111 Page - Freescale Semiconductor, Inc

IMX53CEC 데이터시트(HTML) 111 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL