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IMX53CEC 데이터시트(PDF) 147 Page - Freescale Semiconductor, Inc |
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IMX53CEC 데이터시트(HTML) 147 Page - Freescale Semiconductor, Inc |
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147 / 204 page ![]() Boot Mode Configuration i.MX53xD Applications Processors for Consumer Products, Rev. 2 Freescale Semiconductor 147 5 Boot Mode Configuration This section provides information on boot mode configuration pins allocation and boot devices interfaces allocation. 5.1 Boot Mode Configuration Pins Table 109 provides boot options, functionality, fuse values, and associated pins. Several input pins are also sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse. The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an unblown fuse). For detailed boot mode options configured by the boot mode pins, please refer to the i.MX53xD Fuse Map document and Boot chapter in i.MX53 Reference Manual. Table 108. LDO Voltage Regulators Electrical Specifications Parameter Symbol Min Typ Max Units VDD_DIG_PLL functional Voltage Range1 1 VDD_DIG_PLL and VDD_ANA_PLL voltages are programmable, but should not be set outside the target functional range for proper PLL operation. VVID_DIG_PLL 1.15 1.2 1.3 V VDD_ANA_PLL functional Voltage Range1 VVDD_ANA_PLL 1.7 1.8 1.95 V VDD_DIG_PLL and VDD_ANA_PLL accuracy —— — +/–3 % VDD_DIG_PLL power-supply rejection ratio2 2 The gain or attenuation from the input supply variation to the output of the LDO (by design). —— –18 — dB VDD_ANA_PLL power-supply rejection ratio2 —— –15 — dB Output current3 3 The limitation is for sum of the VDD_DIG_PLL and VDD_ANA_PLL current. IVID_DIG_PLL+ IVDD_ANA_PLL — — 125 mA Table 109. Fuses and Associated Pins Used for Boot Pin Direction at Reset E-Fuse Name Details BOOT_MODE[1] Input N/A Boot Mode selection BOOT_MODE[0] Input |
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