MPC5673K datasheet(110/140 Pages) FREESCALE

110 / 140 page

MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Electrical characteristics

Freescale Semiconductor

110

3.22

Peripheral timing characteristics

3.22.1

SDRAM (DDR)

The MPC5675K memory controller supports three types of DDR devices:

•

DDR-1 (SSTL_2 class II interface)

•

DDR-2 (SSTL_18 interface)

•

LPDDR/Mobile-DDR (1.8V I/O supply voltage)

JEDEC standards define the minimum set of requirements for compliant memory devices:

•

JEDEC STANDARD, DDR2 SDRAM SPECIFICATION, JESD79-2C, MAY 2006

•

JEDEC STANDARD, Double Data Rate (DDR) SDRAM Specification, JESD79E, May 2005

•

JEDEC STANDARD, Low Power Double Data Rate (LPDDR) SDRAM Specification, JESD79-4,

May 2006

The MPC5675K supports the configuration of two output drive strengths for DDR2 and LPDDR:

•

Full drive strength

•

Half drive strength (intended for lighter loads or point-to-point environments)

The MPC5675K memory controller supports dynamic on-die termination in the host device and in the

DDR2 memory device.

This section includes AC specifications for all DDR SDRAM pins. The DC parameters are specified in the

Section 3.19, DRAM pad specifications.

3.22.1.1

DDR and DDR2 SDRAM AC timing specifications

Table 61. DDR and DDR2 (DDR2-400) SDRAM timing specifications

At recommended operating conditions with VDD_MEM_IO of 5%

No.

Symbol

Parameter

Min

Max

Unit

tCK

CC Clock cycle time, CL = x

—90

MHz

VIX-AC

CC MCK AC differential crosspoint voltage1

VDD_MEM_IO

×0.5 –0.1

VDD_MEM_IO

×0.5 +0.1

tCH

CC CK HIGH pulse width1, 2

0.47

0.53

tCK

tCL

CC CK LOW pulse width1, 2

0.47

0.53

tCK

tDQSS

CC Skew between MCK and DQS transitions2, 3

0.25

0.25

tCK

tOS(base)

CC Address and control output setup time relative to

MCK rising edge2, 3

(tCK/2 – 750)

tOH(base)

CC Address and control output hold time relative to

MCK rising edge2, 3

(tCK/2 – 750)

—

tDS1(base)

CC DQ and DM output setup time relative to DQS2, 3

(tCK/4 – 500)

—

tDH1(base)

CC DQ and DM output hold time relative to DQS2, 3

(tCK/4 – 500)

—

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