LPC4350 datasheet(60/145 Pages) NXP

60 / 145 page

LPC4350_30_20_10

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Objective data sheet

Rev. 2.1 — 23 September 2011

60 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

CLK1

T10

[5]

EMC_CLK1 — SDRAM clock 1.

CLKOUT — Clock output pin.

R — Function reserved.

CGU_OUT0 — CGU spare clock output 0.

R — Function reserved.

I2S1_TX_MCLK — I2S1 transmit master clock.

CLK2

D14

141 99

[5]

EMC_CLK3 — SDRAM clock 3.

CLKOUT — Clock output pin.

R — Function reserved.

I/O

SD_CLK — SD/MMC card clock.

EMC_CLK23 — SDRAM clock 2 and clock 3

combined.

I2S0_TX_MCLK — I2S transmit master clock.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the

master and received by the slave. Corresponds to the

signal SCK in the I2S-bus specification.

CLK3

P12

[5]

EMC_CLK2 — SDRAM clock 2.

CLKOUT — Clock output pin.

R — Function reserved.

CGU_OUT1 — CGU spare clock output 1.

R — Function reserved.

I/O

I2S1_RX_SCK — Receive Clock. It is driven by the

master and received by the slave. Corresponds to the

signal SCK in the I2S-bus specification.

Debug pins

DBGEN

[3]

I; PD I

JTAG interface control signal. Also used for boundary

scan.

TCK/SWDCLK

[3]

I; F

Test Clock for JTAG interface (default) or Serial Wire

(SW) clock.

TRST

[3]

I; PU I

Test Reset for JTAG interface.

TMS/SWDIO

[3]

I; PU I

Test Mode Select for JTAG interface (default) or SW

debug data input/output.

TDO/SWO

[3]

Test Data Out for JTAG interface (default) or SW trace

output.

Table 3.

Pin description …continued

LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.

Symbol

Description

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