LPC4350 datasheet(141/145 Pages) NXP

141 / 145 page

LPC4350_30_20_10

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Objective data sheet

Rev. 2.1 — 23 September 2011

141 of 145

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

17. Revision history

Table 30.

Revision history

Document ID

Release date Data sheet status

Change notice

Supersedes

LPC4350_30_20_10 v.2.1

20110923

Objective data sheet

LPC4350_30_20_10 v.2

Modifications:

• LQFP100 package added in Table 3.

• Pin P2_7 designated as ISP entry pin.

• Boot pins corrected in Table 3 and Table 5: Pin P2_7 replaced by pin

P2_9 as boot pin. Pin level corrected for 4th boot pin (pin P2_9) in

Table 5.

• USART3 boot mode added in Table 5.

• Description of ISP mode added (Section 7.11).

• VI updated for I/O pins (see Table 6).

• Table 2 updated.

• Pin description of Pin P2_2 updated: Function CTOUT_6 changed to

CTIN_6.

• Pin description of Pin PF_9 updated: Function SGPIO7 changed to

SGPIO3.

• LQFP208 package added in Table 3.

• SPIFI memory added in Figure 9.

• AHB multilayer matrix connections updated in Figure 8.

• Pin P7_2, column LQFP144: replaced 113 by 115 in Table 3.

LPC4350_30_20_10 v.2

20110714

Objective data sheet

LPC4350_30_20_10 v.1

20101029

Objective data sheet

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