AFS090 datasheet(222/334 Pages) MICROSEMI

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Device Architecture

2- 20 6

R e v isio n 2

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

Fusion devices support Class II. This provides a differential amplifier input buffer and a push-pull output

buffer.

Timing Characteristics

Table 2-153 • Minimum and Maximum DC Input and Output Levels

HSTL Class II

VIL

VIH

VOL

VOH

IOL IOH

IOSL

IOSH IIL1 IIH2

Drive Strength

Min.

Max.

Min.

Max.

Min.

VmA mA

Max.

mA3

Max.

mA3

µA4 µA4

15 mA3

–0.3 VREF – 0.1 VREF + 0.1

3.6

0.4

VCCI – 0.4 15

Note:

1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.

2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is

larger when operating outside recommended ranges.

3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

4. Currents are measured at 85°C junction temperature.

5. Output drive strength is below JEDEC specification.

Figure 2-127 • AC Loading

Table 2-154 • AC Waveforms, Measuring Points, and Capacitive Loads

Input Low (V)

Input High (V)

Measuring Point* (V)

VREF (typ.) (V)

VTT (typ.) (V)

CLOAD (pF)

VREF – 0.1

VREF + 0.1

0.75

Note:

*Measuring point = Vtrip. See Table 2-90 on page 2-168 for a complete table of trip points.

Test Point

20 pF

HSTL

Class II

VTT

Table 2-155 • HSTL Class II

Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI = 1.4 V, VREF = 0.75 V

Speed

Grade

tDOUT

tDP

tDIN

tPY

tEOUT

tZL

tZH

tLZ

tHZ

tZLS

tZHS

Units

Std.

0.66

3.02

0.04

2.12

0.43

3.08

2.71

5.32

4.95

–1

0.56

2.57

0.04

1.81

0.36

2.62

2.31

4.52

4.21

–2

0.49

2.26

0.03

1.59

0.32

2.30

2.03

3.97

3.70

Note:

For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on

page 3-9.

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