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R5F10RF8AFP 데이터시트(PDF) 26 Page - Renesas Technology Corp

부품명 R5F10RF8AFP
상세설명  Integrated LCD controller/driver, True Low Power Platform (as low as 75 關A/MHz, and 0.64 關A for RTC LVD), 1.6 V to 5.5 V operation, 8 to 32 Kbyte Flash, 31 DMIPS at 24 MHz, for All LCD Based Applications
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F10RF8AFP 데이터시트(HTML) 26 Page - Renesas Technology Corp

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RL78/L12
2. ELECTRICAL SPECIFICATIONS (TARGET)
Page 26 of 73
R01DS0157EJ0001 Rev.0.01
2012.02.20
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
Caution
The pins mounted depend on the product.
Refer to 1.3.1
32-pin products to 1.3.5
64-pin
products.
(TA =
−40 to +85°C, 1.6 V ≤ EVDD = VDD ≤ 5.5 V, VSS = EVSS = 0 V)
Items
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120,
P125 to P127, P140 to P147
Normal input buffer 0.8EVDD
EVDD
V
TTL input buffer
4.0 V
≤ EVDD ≤ 5.5 V
2.2
EVDD
V
TTL input buffer
3.3 V
≤ EVDD < 4.0 V
2.0
EVDD
V
VIH2
P10, P11, P15, P16
TTL input buffer
1.6 V
≤ EVDD < 3.3 V
1.50
EVDD
V
VIH3
P20, P21
0.7VDD
VDD
V
VIH4
P60, P61
0.7EVDD
6.0
V
Input voltage,
high
VIH5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0.8VDD
VDD
V
VIL1
P10 to P17, P30 to P32, P40 to P43,
P50 to P54, P70 to P74, P120,
P125 to P127, P140 to P147
Normal input buffer
0
0.2EVDD
V
TTL input buffer
4.0 V
≤ EVDD ≤ 5.5 V
0
0.8
V
TTL input buffer
3.3 V
≤ EVDD < 4.0 V
0
0.5
V
VIL2
P10, P11, P15, P16
TTL input buffer
1.6 V
≤ EVDD < 3.3 V
0
0.32
V
VIL3
P20, P21
0
0.3VDD
V
VIL4
P60, P61
0
0.3EVDD
V
Input voltage,
low
VIL5
P121 to P124, P137, EXCLK, EXCLKS, RESET
0
0.2VDD
V
Cautions
The maximum value of VIH of P10, P12, P15, P17 is VDD, even in the N-ch open-drain mode.
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the
port pins.



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