AD9557SLASHPCBZ datasheet(89/92 Pages) AD

89 / 92 page

Data Sheet

AD9557

Rev. A | Page 89 of 92

Table 120. EEPROM Storage Sequence for Operational Control Settings

Address

Bits

Bit Name

Description

0x0E37

[7:0]

Operational controls

The default value of this register is 0x0D, which the controller interprets as a data instruction. Its

decimal value is 13, so this tells the controller to transfer 14 bytes of data (13 + 1), beginning at

the address specified by the next two bytes. The controller stores 0x0D in the EEPROM and

increments the EEPROM address pointer.

0x0E38

[7:0]

0x0E39

[7:0]

The default value of these two registers is 0x0A00. Note that Register 0x0E38 and Register 0x0E39

are the most significant and least significant bytes of the target address, respectively. Because

the previous register contains a data instruction, these two registers define a starting address

(in this case, 0x0A00). The controller stores 0x0A00 in the EEPROM and increments the EEPROM

pointer by 2. It then transfers 14 bytes from the register map (beginning at Address 0x0A00) to

the EEPROM and increments the EEPROM address pointer by 15 (14 data bytes and one checksum

byte). The 14 bytes transferred correspond to the operational controls parameters in the register map.

Table 121. EEPROM Storage Sequence for APLL Calibration

Address

Bits

Bit Name

Description

0x0E3A

[7:0]

Calibrate APLL

The default value of this register is 0xA0, which the controller interprets as a calibrate instruction.

The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer.

0x0E3B

[7:0]

I/O update

The default value of this register is 0x80, which the controller interprets as an I/O update instruction.

The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.

Table 122. EEPROM Storage Sequence for End of Data

Address

Bits

Bit Name

Description

0x0E3C

[7:0]

End of data

The default value of this register is 0xFF, which the controller interprets as an end instruction.

The controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and

enters an idle state.

Note that if this is a pause rather than an end instruction, the controller actions are the same

except that the controller increments the EEPROM address pointer rather than resetting it.

Table 123. Available for Additional EEPROM Instructions

Address

Bits

Bit Name

Description

0x0E3D

to 0xE45

[7:0]

Unused

This area is available for additional EEPROM instructions.

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