ADP1053ACPZ-R7 datasheet(63/84 Pages) AD

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Data Sheet

ADP1053

Rev. A | Page 63 of 84

Table 83. Register 0xFE3D—Channel B Modulation Limit

Bits

Bit Name

R/W

Description

This register sets the maximum duty cycle modulation limit for PWM outputs in Channel B.

The modulation limit is the maximum time variation for the modulated edges from the default

timing (see Figure 42). The step size of an LSB depends on the switching frequency.

Switching Frequency

LSB Step Size

48.8 kHz to 86.8 kHz

80 ns

97.7 kHz to 183.8 kHz

40 ns

195.3 kHz to 378.8 kHz

20 ns

[7:0]

Channel B

modulation limit

R/W

390.6 kHz to 625.0 kHz

10 ns

Table 84. Register 0xFE3E—Channel A Feedforward and Soft Start Digital Filter Setting

Bits

Bit Name

R/W

Description

[7:6]

Reserved

R/W

Reserved.

High frequency ADC

debounce time

R/W

This bit sets the debounce time for detecting the settling of the VS_A high frequency ADC.

Bit 4 must be set to 1.

0 = 5 ms.

1 = 10 ms.

High frequency ADC

debounce enable

R/W

Setting this bit enables a debounce time for detecting the settling of the VS_A high frequency

ADC at the end of a soft start. The debounce time is set using Bit 5.

Feedforward ADC

selection

R/W

This bit should be set to 1 (factory default setting). This bit selects the 11-bit ACSNS ADC for

feedforward control of Channel A. Do not set this bit to 0.

Feedforward enable

R/W

This bit enables or disables feedforward control on Channel A.

0 = feedforward control disabled on Channel A.

1 = feedforward control enabled on Channel A.

These bits set the low-pass filter gain for Channel A during soft start.

Bit 1

Bit 0

Soft Start Filter Gain

[1:0]

Soft start filter gain

R/W

Table 85. Register 0xFE3F—Channel B Feedforward and Soft Start Digital Filter Setting

Bits

Bit Name

R/W

Description

[7:6]

Reserved

R/W

Reserved.

High frequency ADC

debounce time

R/W

This bit sets the debounce time for detecting the settling of the VS_B high frequency ADC.

Bit 4 must be set to 1.

0 = 5 ms.

1 = 10 ms.

High frequency ADC

debounce enable

R/W

Setting this bit enables a debounce time for detecting the settling of the VS_B high frequency

ADC at the end of a soft start. The debounce time is set using Bit 5.

Feedforward ADC

selection

R/W

This bit should be set to 1 (factory default setting). This bit selects the 11-bit ACSNS ADC for

feedforward control of Channel B. Do not set this bit to 0.

Feedforward enable

R/W

This bit enables or disables feedforward control on Channel B.

0 = feedforward control disabled on Channel B.

1 = feedforward control enabled on Channel B.

These bits set the low-pass filter gain for Channel B during soft start.

Bit 1

Bit 0

Soft Start Filter Gain

[1:0]

Soft start filter gain

R/W

ADP1053ACPZ-R7 데이터시트(PDF) 63 Page - Analog Devices

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