ADP1053ACPZ-R7 datasheet(70/84 Pages) AD

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ADP1053

Data Sheet

Rev. A | Page 70 of 84

Table 102. Register 0xFE6C—CS1_B Blanking Reference Edge

Bits

Bit Name

R/W

Description

[7:4]

Reserved

R/W

Reserved.

OUT6 rising edge

blanking

R/W

This bit specifies whether the blanking time for the CS1_B OCP comparator is referenced to the

rising edge of OUT6.

0 = no blanking at OUT6 rising edge.

1 = blanking time referenced to OUT6 rising edge.

OUT5 rising edge

blanking

R/W

This bit specifies whether the blanking time for the CS1_B OCP comparator is referenced to the

rising edge of OUT5.

0 = no blanking at OUT5 rising edge.

1 = blanking time referenced to OUT5 rising edge.

OUT2 rising edge

blanking

R/W

This bit specifies whether the blanking time for the CS1_B OCP comparator is referenced to the

rising edge of OUT2.

0 = no blanking at OUT2 rising edge.

1 = blanking time referenced to OUT2 rising edge.

OUT1 rising edge

blanking

R/W

This bit specifies whether the blanking time for the CS1_B OCP comparator is referenced to the

rising edge of OUT1.

0 = no blanking at OUT1 rising edge.

1 = blanking time referenced to OUT1 rising edge.

Table 103. Register 0xFE6D—OUT3, OUT4, OUT7, and OUT8 Cycle-by-Cycle OCP Response

Bits

Bit Name

R/W

Description

[7:4]

Reserved

R/W

Reserved.

OUT8 cycle-by-cycle

OCP response

R/W

When this bit is set, an OCP signal on the channel to which OUT8 is assigned causes OUT8 to

turn on. The falling edge of the SR output still follows the programmed value.

OUT7 cycle-by-cycle

OCP response

R/W

When this bit is set, an OCP signal on the channel to which OUT7 is assigned causes OUT7 to

turn on. The falling edge of the SR output still follows the programmed value.

OUT4 cycle-by-cycle

OCP response

R/W

When this bit is set, an OCP signal on the channel to which OUT4 is assigned causes OUT4 to

turn on. The falling edge of the SR output still follows the programmed value.

OUT3 cycle-by-cycle

OCP response

R/W

When this bit is set, an OCP signal on the channel to which OUT3 is assigned causes OUT3 to

turn on. The falling edge of the SR output still follows the programmed value.

Table 104. Register 0xFE6E—CS Gain Trim

Bits

Bit Name

R/W

Description

Gain polarity

R/W

1 = negative gain is introduced.

0 = positive gain is introduced.

[6:0]

CS gain trim

R/W

This value calibrates the primary side current sense gain. For more information, see the CS,

CS1_A, and CS1_B Gain Trim section.

Table 105. Register 0xFE6F—CS OCP Settings

Bits

Bit Name

R/W

Description

CS OCP ignored

R/W

Setting this bit causes the CS OCP comparator output to be ignored. The flag is always cleared.

These bits specify the blanking time. During this time, the CS OCP comparator output is

ignored. The CS OCP blanking time is measured from OUT1 and OUT2.

Bit 6

Bit 5

Bit 4

Leading Edge Blanking Time

0 ns

40 ns

80 ns

120 ns

200 ns

400 ns

600 ns

[6:4]

Leading edge

blanking

R/W

800 ns

ADP1053ACPZ-R7 데이터시트(PDF) 70 Page - Analog Devices

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