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SSM2518CPZ-R7 데이터시트(PDF) 29 Page - Analog Devices

부품명 SSM2518CPZ-R7
상세설명  Digital Input Stereo, 2 W, Class-D
PDF  48 Pages
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SSM2518CPZ-R7 데이터시트(HTML) 29 Page - Analog Devices

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Data Sheet
SSM2518
Rev. A | Page 29 of 48
SERIAL AUDIO INTERFACE CONTROL REGISTER
Address: 0x03, Reset: 0x00, Name: Serial_Interface_Control
Table 16. Bit Descriptions for Serial_Interface_Control
Bits
Bit Name
Settings
Description
Reset
Access
7
BCLK_GEN
Internal BCLK Generator Enable.
0x0
RW
0
Bit clock from BCLK pin is used
1
Internally generated bit clock is used
6
LRCLK_MODE
LRCLK Shape Selection. Required only for TDM modes.
0x0
RW
0
50% duty cycle
1
1-bit pulse
5
LRCLK_POL
LRCLK Polarity.
0x0
RW
0
Rising edge (normal)
1
Falling edge (inverted)
4
SAI_MSB
Serial Data Bit Order.
0x0
RW
0
MSB first
1
LSB first
[3:2]
SLOT_WIDTH
TDM Slot Width. Required only for TDM modes.
0x0
RW
00
32 BCLK cycles per slot
01
24 BCLK cycles per slot
10
16 BCLK cycles per slot
11
Reserved
1
BCLK_EDGE
BCLK Active Edge.
0x0
RW
0
Rising BCLK edge used
1
Falling BCLK edge used
0
RESERVED
Reserved.
0x0
RW



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