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SSM2518CPZ-R7 데이터시트(PDF) 27 Page - Analog Devices

부품명 SSM2518CPZ-R7
상세설명  Digital Input Stereo, 2 W, Class-D
PDF  48 Pages
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SSM2518CPZ-R7 데이터시트(HTML) 27 Page - Analog Devices

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Data Sheet
SSM2518
Rev. A | Page 27 of 48
EDGE SPEED AND CLOCKING CONTROL REGISTER
Address: 0x01, Reset: 0x00, Name: Edge_Clock_Control
Table 14. Bit Descriptions for Edge_Clock_Control
Bits
Bit Name
Settings
Description
Reset
Access
[7:3]
RESERVED
Reserved.
0x00
RW
[2:1]
EDGE
Edge Rate Control. This limits the edge rate of the switching output stage.
The low EMI operation modes reduce the edge speed, lowering EMI and
power efficiency.
0x0
RW
00
No edge rate control
01
Low EMI
10
Lower EMI
11
Lowest EMI
0
ASR
Automatic Sample Rate Detection.
0x0
RW
0
Automatic detection enabled
1
Manual sample rate selection given by FS field, Bits[1:0] of Register 0x02



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