FXOS8700CQ datasheet(73/86 Pages) FREESCALE

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Freescale Semiconductor, Inc.

Figure 122. DBCNTM bit function

9.17

Magnetometer control registers

9.17.1

M_CTRL_REG1 (0x5B) register

m_acal

m_rst

m_ost

m_os[2:0]

m_hms[1:0]

0b000

0b00

Figure 123. M_CTRL_REG1 register

Table 93. M_CTRL_REG1 bit descriptions

Field

Description

m_acal

Magnetic hard-iron offset auto-calibration enable:

0: Auto-calibration feature disabled

1: Auto-calibration feature is enabled; the ASIC uses the maximum and minimum magnetic data to determine the

hard iron offset value. The M_OFF_X/Y/Z registers are automatically loaded with (MAX_X/Y/Z + MIN_X/Y/Z)/2 for

each axis at the end of every ODR cycle.

m_rst

One-shot magnetic reset de-gauss control bit:

0: No magnetic sensor reset is active

1: One-shot magnetic reset is enabled, hardware cleared when complete.

Magnetic Event

Count Threshold

FF Counter

Magnetic Event

Count Threshold

(a)

Debounce Counter

Magnetic Event

Count Threshold

MAG_THS_X_MSB[m_ths_dbcntm] = 1

(b)

MAG_THS_X_MSB[m_ths_dbcntm] = 0

(c)

Debounce Counter

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