전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

CY2DP818ZXC 데이터시트(PDF) 7 Page - Cypress Semiconductor

부품명 CY2DP818ZXC
상세설명  1:8 Clock Fanout Buffer
PDF  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2DP818ZXC 데이터시트(HTML) 7 Page - Cypress Semiconductor

Back Button CY2DP818ZXC Datasheet HTML 3Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 4Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 5Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 6Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 7Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 8Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 9Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 10Page - Cypress Semiconductor CY2DP818ZXC Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 13 page
background image
CY2DP818
Document Number: 38-07061 Rev. *D
Page 7 of 13
AC Switching Characteristics
Table 7. LVPECL Output, VDD = 3.3 V ± 5%, TA = 0 C to 70C or –40 C to 85 C
Parameter
Description
Conditions
Min
Typ
Max
Unit
VOD
Driver Differential Output voltage
p-p
VDD = Min, VIN = VIH or VIL,
RL = 50 
1000
3600
mV
VOC
Driver common-mode p-p
VDD = Min, VIN = VIH or VIL,
RL = 50 
––
300
mV
tR
Rise Time
Differential 20% to 80%,
CL = 10 pF to GND,
RL = 50  to GND
300
1200
ps
tF
Fall Time
VOH
Output High Voltage
VDD = Min, VIN = VIH or VIL,
IOH = –12 mA
2.1
3.0
V
VOL[2]
Output Low Voltage
VDD = Min, VIN = VIH or VIL
0.8
1.3
V
IOS
Short Circuit Current
VDD = Max, VOUT = GND
–125
–150
mA
Table 8. VDD = 3.3 V ± 5%, TA = 0 C to 70 C or –40 C to 85 C
Parameter
Description
Conditions
Min
Typ
Max
Unit
tPLH
Propagation Delay – Low to High VID = 100 mV
3
4
5
ns
tPHL
Propagation Delay – High to Low VID = 100 mV
3
4
5
ns
tSK(0)
Output Skew: Skew between
outputs of the same package
(in phase)
0.2
ns
tSK(p)
Pulse Skew: Skew between
opposite transitions of the same
output (tPHL–tPLH)
0.2
ns
tSK(t)
Package Skew: Skew between
outputs of different packages at
the same power supply voltage,
temperature and package type.
Same input signal level and
output load.
VID = 100 mV
1
ns
Table 9. High frequency Parametrics
Parameter
Description
Conditions
Min
Typ
Max
Unit
Fmax
Maximum frequency
VDD = 3.3 V
45%–55% duty cycle
Standard load circuit
350
MHz
Note
2. VOL levels are dependent on the termination voltage VTT and termination resistance RTT. Changing either of these values will affect VOL.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com