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CY2DP818ZXC 데이터시트(PDF) 1 Page - Cypress Semiconductor |
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CY2DP818ZXC 데이터시트(HTML) 1 Page - Cypress Semiconductor |
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1 / 13 page ![]() CY2DP818 1:8 Clock Fanout Buffer Cypress Semiconductor Corporation • 198 Champion Court • San Jose , CA 95134-1709 • 408-943-2600 Document Number: 38-07061 Rev. *D Revised August 20, 2012 1:8 Clock Fanout Buffer Features ■ Low-voltage operation VDD = 3.3 V ■ 1:8 fanout ■ Operation to350 MHz ■ Single input configurable for LVDS, LVPECL, or LVTTL ■ 8 pair of LVPECL outputs ■ Drives a 50 ohm load ■ Low input capacitance ■ Low output skew ■ Low propagation delay (tpd = 4 ns, typical) ■ Commercial and Industrial temperature ranges ■ 38-pin TSSOP Package Description The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals. The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input. Logic Block Diagram INPUT (LVPECL / LVDS / LVTTL) OUTPUT (LVPECL) Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B INPUT A INPUT B InConfig |
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