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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETX15VE 데이터시트(PDF) 89 Page - Texas Instruments |
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TNETX15VE 데이터시트(HTML) 89 Page - Texas Instruments |
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89 / 113 page  TNETX15VE VLAN-ENGINE ADDRESS-LOOKUP DEVICE SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997 89 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION masking interrupts The programmer may be interested in processing some interrupts now, while leaving the others for a later time. The TNETX15VE can mask interrupts. This is accomplished by an interrupt masking register, (intmask). The int and intmask registers have a one-to-one correspondence. The only way EINT is asserted is if both int and intmask are in a 1 state. The logic for the interrupt masking is shown in Figure 17. Int Register Intmask Register AND AND OR EINT Interrupt Mask Register Interrupt Register Figure 17. Interrupt Masking Logic test interrupts (INT) Test interrupts are generated by asserting the INT bit in the int register. The INT bit in the intmask register must also be set to a 1 state for the interrupt to take effect. The INT bit is used to give the programmer an easy way to test interrupt detection. This bit is the only bit in the int register that is writeable. |
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