SPC564L54L5 datasheet(16/160 Pages) STMICROELECTRONICS

16 / 160 page

Introduction

SPC56XL60/54

16/160

Doc ID 15457 Rev 8

The following functions are implemented:

●

ECC encoding (32-bit boundary for data and complete address bus)

●

ECC decoding (32-bit boundary and entire address)

●

Address translation from the AHB protocol on the XBAR to the SRAM array

The platform SRAM controller is replicated for each processor.

1.5.9

Memory subsystem access time

Every memory access the CPU performs requires at least one system clock cycle for the

data phase of the access. Slower memories or peripherals may require additional data

phase wait states. Additional data phase wait states may also occur if the slave being

accessed is not parked on the requesting master in the crossbar.

Table 2 shows the number of additional data phase wait states required for a range of

memory accesses.

1.5.10

Error Correction Status Module (ECSM)

The ECSM on this device manages the ECC configuration and reporting for the platform

memories (flash memory and SRAM). It does not implement the actual ECC calculation. A

detected error (double error for flash memory or SRAM) is also reported to the FCCU. The

following errors and indications are reported into the ECSM dedicated registers:

●

ECC error status and configuration for flash memory and SRAM

●

ECC error reporting for flash memory

●

ECC error reporting for SRAM

●

ECC error injection for SRAM

Table 2.

Platform memory access time summary

AHB transfer

Data phase

wait states

Description

e200z4d instruction fetch

Flash memory prefetch buffer hit (page hit)

e200z4d instruction fetch

Flash memory prefetch buffer miss

(based on 4-cycle random flash array access time)

e200z4d data read

0–1

SRAM read

e200z4d data write

SRAM 32-bit write

e200z4d data write

SRAM 64-bit write (executed as 2 x 32-bit writes)

e200z4d data write

0–2

SRAM 8-,16-bit write

(Read-modify-Write for ECC)

e200z4d flash memory read

Flash memory prefetch buffer hit (page hit)

e200z4d flash memory read

Flash memory prefetch buffer miss (at 120 MHz; includes 1 cycle

of program flash memory controller arbitration)

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