ST10F280_12 datasheet(160/239 Pages) STMICROELECTRONICS

160 / 239 page

CAN modules

ST10F280

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Doc ID 8673 Rev. 3

Note:

Reading the upper half of the Control Register (status partition) will clear the Status Change

Interrupt value in the Interrupt Register, if it is pending. Use byte accesses to the lower half

to avoid this.

15.4

CAN interrupt handling

The on-chip CAN Module has one interrupt output, which is connected (through a

synchronization stage) to a standard interrupt node in the ST10F280 in the same manner as

all other interrupts of the standard on-chip peripherals. The control register for this interrupt

is XP0IC (located at address F186h/C3h for CAN1 and F18Eh/C7h for CAN2 in the ESFR

range). The associated interrupt vector is called XP0INT at location 100h (trap number 40h)

and XP1INT at location 104h (trap number 41h). With this configuration, the user has all

control options available for this interrupt, such as enabling/disabling, level and group

priority, and interrupt or PEC service (see note below).

LEC Last Error Code

This field holds a code which indicates the type of the last error occurred on the CAN bus.

If a message has been transferred (reception or transmission) without error, this field will

be cleared. Code “7” is unused and may be written by the CPU to check for updates.

0: No Error

1: Stuff Error: More than 5 equal bit in a sequence have occurred in a part of a received

message where this is not allowed.

2: Form Error: A fixed format part of a received frame has the wrong format.

3: AckError: The message this CAN controller transmitted was not acknowledged by

another node

4: Bit1Error: During the transmission of a message (with the exception of the arbitration

field), the device wanted to send a recessive level (“1”), but the monitored bus value was

dominant

5: Bit0Error: During the transmission of a message (or acknowledge bit, active error flag,

or overload flag), the device wanted to send a dominant level (“0”), but the monitored bus

value was recessive. During busoff recovery this status is set each time a sequence of 11

recessive bit has been monitored. This enables the CPU to monitor the proceeding of the

busoff recovery sequence (indicating the bus is not stuck at dominant or continuously

disturbed).

6: CRCError: The CRC check sum was incorrect in the message received.

TXOK Transmitted Message Successfully

Indicates that a message has been transmitted successfully (error free and acknowledged

by at least one other node), since this bit was last reset by the CPU (the CAN controller

does not reset this bit!).

RXOK Received Message Successfully

Indicates that a message has been received successfully, since this bit was last reset by

the CPU (the CAN controller does not reset this bit!).

EWRN Error Warning Status

Indicates that at least one of the error counters in the EML has reached the error warning

limit of 96.

BOFF Busoff Status

Indicates when the CAN controller is in busoff state (see EML).

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