ST10F280_12 datasheet(162/239 Pages) STMICROELECTRONICS

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CAN modules

ST10F280

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Doc ID 8673 Rev. 3

15.4.1

Bit timing configuration

According to the CAN protocol specification, a bit time is subdivided into four segments:

Sync segment, propagation time segment, phase buffer segment 1 and phase buffer

segment 2.

Each segment is a multiple of the time quantum tq with tq = ( BRP + 1 ) x2 xtXCLK

The Synchronization Segment (Sync seg) is always 1 tq long. The Propagation Time

Segment and the Phase Buffer Segment1 (combined to Tseg1) defines the time before the

sample point, while Phase Buffer Segment2 (Tseg2) defines the time after the sample point.

The length of these segments is programmable (except Sync-Seg).

Note:

For exact definition of these segments please refer to the CAN Specification.

Figure 63.

Bit timing definition

Message 15 Interrupt: Bit INTPND in the Message Control Register of message object 15

(last message) has been set. The last message object has the highest interrupt priority of

all message objects. 1) (1)

(2+N)

Message N Interrupt: Bit INTPND in the Message Control Register of message object ‘N’

has been set (N = 1...14). (1)(2)

Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority

the possibility to update INTID or to reset INTID to 00h (idle state).

A message interrupt code is only displayed, if there is no other interrupt request with a higher priority.

Table 31.

INTID values and corresponding interrupt sources (continued)

INTID

Cause of the Interrupt

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