ST10F280_12 datasheet(169/239 Pages) STMICROELECTRONICS

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ST10F280

Watchdog timer

Doc ID 8673 Rev. 3

169/239

Watchdog timer

The Watchdog Timer is a fail-safe mechanism which prevents the microcontroller from

malfunctioning for long periods of time.

The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in

the time interval until the EINIT (end of initialization) instruction has been executed.

Therefore, the chip start-up procedure is always monitored. The software must be designed

to service the watchdog timer before it overflows. If, due to hardware or software related

failures, the software fails to do so, the watchdog timer overflows and generates an internal

hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components

to be reset.

Each of the different reset sources is indicated in the WDTCON register.

The indicated bit are cleared with the EINIT instruction. The origine of the reset can be

identified during the initialization phase.

WDTCON

Address:

0xFFAEh / D7h SFR

Reset:

0x00XXh

Type:

R, R/W

76543210

WDTREL

PONR

LHWR

SHWR

SWR

WDTR

WDTIN

R/W

RRRRR

R/W

WDTIN Watchdog Timer Input Frequency Selection

0: Input Frequency is fCPU/2.

1: Input Frequency is fCPU/128.

WDTR(1)

More than one reset indication flag may be set. After EINIT, all flags are cleared.

Watchdog Timer Reset Indication Flag

Set by the watchdog timer on an overflow.

Cleared by a hardware reset or by the SRVWDT instruction.

SWR(1) Software Reset Indication Flag

Set by the SRST execution.

Cleared by the EINIT instruction.

SHWR(1) Short Hardware Reset Indication Flag

Set by the input RSTIN.

Cleared by the EINIT instruction.

LHWR(1) Long Hardware Reset Indication Flag

Set by the input RSTIN.

Cleared by the EINIT instruction.

PONR(1)(2)

Power-on is detected when a rising edge from Vcc = 0 V to Vcc > 2.0 V is recognized.

Power-On (Asynchronous) Reset Indication Flag

Set by the input RSTIN if a power-on condition has been detected.

Cleared by the EINIT instruction.

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