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ST10F280 데이터시트(PDF) 173 Page - STMicroelectronics |
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ST10F280 데이터시트(HTML) 173 Page - STMicroelectronics |
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173 / 239 page ![]() ST10F280 System reset Doc ID 8673 Rev. 3 173/239 Figure 66. Synchronous warm reset (short low pulse on RSTIN) 1. RSTIN assertion can be released there. 2. If during the reset condition (RSTIN low), VRPD voltage drops below the threshold voltage (about 2.5V for 5V operation), the asynchronous reset is then immediately entered. 3. RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on (fCPU =fXTAL / 2), else it is 4 CPU clock cycles (8 TCL). 4. RSTIN pin is pulled low if bit BDRSTEN (bit 5 of SYSCON register) was previously set by software. Bit BDRSTEN is cleared after reset. |
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