S29GL01GS datasheet(41/104 Pages) SPANSION

41 / 104 page

March 16, 2012 S29GL_128S_01GS_00_06

GL-S MirrorBit® Family

Data

She e t

5.4.2.5

Reading Toggle Bits DQ6/DQ2

Refer to Figure 5.5 on page 39 for the following discussion. Whenever the system initially begins reading

toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling.

Typically, the system would note and store the value of the toggle bit after the first read. After the second

read, the system would compare the new value of the toggle bit with the previous value. If the toggle bit is not

toggling, the device has completed the program or erases operation. The system can read array data on

DQ15-DQ0 on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is High (see DQ5: Exceeded Timing Limits on page 41). If

it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have

stopped toggling just as DQ5 went High. If the toggle bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is still toggling, the device did not complete the operation

successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not

gone High. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,

determining the status as described in the previous paragraph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the beginning of the algorithm when it returns to

determine the status of the operation (top of Figure 5.6 on page 41).

Figure 5.6 Toggle Bit Program

Notes:

1. Read toggle bit twice to determine whether or not it is toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.

5.4.2.6

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was

not successfully completed. The system must issue the reset command to return the device to reading array

data.

When a timeout occurs, the software must send a reset command to clear the timeout bit (DQ5) and to return

the EAC to read array mode. In this case, it is possible that the flash will continue to communicate busy for up

to 2 µs after the reset command is sent.

START

Read DQ7 -DQ0 (Note 1)

Erase/Program

Operation Not

Complete

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

Read DQ7 -DQ0 Twice (Notes 1, 2)

Toggle Bit

= Toggle?

Yes

Erase/Program

Operation Complete

Read DQ7 -DQ0

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