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S29GL01GS 데이터시트(PDF) 81 Page - SPANSION

부품명 S29GL01GS
상세설명  GL-S MirrorBit짰 Eclipse??Flash Non-Volatile Memory Family
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March 16, 2012 S29GL_128S_01GS_00_06
GL-S MirrorBit® Family
81
Data
She e t
Note:
1. Not 100% tested.
Figure 10.5 Back to Back Read (tACC) Operation Timing Diagram
Figure 10.6 Back to Back Read Operation (tRC)Timing Diagram
Note:
Back to Back operations, in which CE# remains Low between accesses, requires an address change to initiate the second access.
Table 10.5 Read Operation VIO = VCC = 2.7V to 3.6V (-40°C to +105°C)
Parameter
Description
Test Setup
Speed Option
Unit
JEDEC
Std
100
110
120
tAVAV
tRC
Read Cycle Time (Note 1)
128 Mb, 256 Mb
Min
100
110
ns
512 Mb, 1 Gb
110
120
tAVQV
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
128 Mb, 256 Mb
Max
100
110
ns
512 Mb, 1 Gb
110
120
tELQV
tCE
Chip Enable to Output
Delay
OE# = VIL
128 Mb, 256 Mb
Max
100
110
ns
512 Mb, 1 Gb
110
120
tPACC
Page Access Time
128 Mb, 256 Mb
Max
15
20
ns
512 Mb, 1 Gb
15
20
tGLQV
tOE
Output Enable to Output Delay
Max
25
ns
tAXQX
tOH
Output Hold time from addresses, CE# or
OE#, Whichever Occurs First
Min
0
ns
tEHQZ
tDF
Chip Enable or Output Enable to Output
High-Z (Note 1)
Max
15
ns
tOEH
Output Enable Hold Time
(Note 1)
Read
Min
0
ns
Toggle and
Data# Polling
Min
10
ns
tASSB
Automatic Sleep to Standby time (Note 1)
CE# = VIL, Address
stable
Typ
5
µs
Max
8
µs
Amax-A0
CE#
OE#
DQ15-DQ0
tACC
tOE
tCE
tDF
tDF
tOH
tOH
tOH
Amax-A0
CE#
OE#
DQ15-DQ0
tRC
tACC
tOE
tCE
tDF
tOH
tOH



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