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S29GL01GS 데이터시트(PDF) 24 Page - SPANSION |
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S29GL01GS 데이터시트(HTML) 24 Page - SPANSION |
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24 / 104 page ![]() 24 GL-S MirrorBit® Family S29GL_128S_01GS_00_06 March 16, 2012 Da ta Sh e e t 4. Read Operations 4.1 Asynchronous Read Each read access may be made to any location in the memory (random access). Each random access is self- timed with the same latency from CE# or address to valid data (tACC or tCE). 4.2 Page Mode Read Each random read accesses an entire 32-byte Page in parallel. Subsequent reads within the same Page have faster read access speed. The Page is selected by the higher address bits (A MAX-A4), while the specific word of that page is selected by the least significant address bits A3-A0. The higher address bits are kept constant and only A3-A0 changed to select a different word in the same Page. This is an asynchronous access with data appearing on DQ15-DQ0 when CE# remains Low, OE# remains Low, and the asynchronous Page access time (tPACC) is satisfied. If CE# goes High and returns Low for a subsequent access, a random read access is performed and time is required (tACC or tCE). |
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