| 전자부품 데이터시트 검색엔진 |
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CXR702F080 데이터시트(PDF) 13 Page - Sony Corporation |
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CXR702F080 데이터시트(HTML) 13 Page - Sony Corporation |
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13 / 32 page ![]() – 13 – CXR702F080 Pin Circuit format After a reset Port G data MPX RD CT0ED0, CT0ED1 CT1ED0, CT1ED1 CT2ED0, CT2ED1 Port G direction "0" after a reset Input data latch Internal data bus IP CMOS Schmitt input Pull-up resistor "0" after a reset Port H data MPX RD Port H direction "0" after a reset Port H function select "0" after a reset Input data latch Internal data bus MPX TxD0, TxD1 IP Pull-up resistor "0" after a reset Port H data MPX RD RxD0, RxD1 Port H direction "0" after a reset Input data latch Internal data bus IP CMOS Schmitt input Pull-up resistor "0" after a reset PG0/CT0ED0 PG1/CT0ED1 PG2/CT1ED0 PG3/CT1ED1 PG4/CT2ED0 PG5/CT2ED1 Hi-Z PH1/RxD0 PH3/RxD1 Hi-Z PH0/TxD0 PH2/TxD1 Hi-Z |
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