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WM8980CGEFL/V 데이터시트(PDF) 63 Page - Wolfson Microelectronics plc

부품명 WM8980CGEFL/V
상세설명  Stereo CODEC with Speaker Driver and Video Buffer
PDF  123 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8980CGEFL/V 데이터시트(HTML) 63 Page - Wolfson Microelectronics plc

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Pre-Production
WM8980
w
PP, Rev 3.8, May 2012
63
ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output
PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This
is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital
and is equal to 2
21 * input clock period.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R7
Additional
Control
0
SLOWCLKEN
0
Slow clock enable. Used for both the
jack insert detect debounce circuit and
the zero cross timeout.
0 = slow clock disabled
1 = slow clock enabled
Table 45 Timeout Clock Enable Control
OUT3/OUT4 MIXERS AND OUTPUT STAGES
The OUT3/OUT4 pins can provide an additional stereo line output, a mono output, or a pseudo
ground connection for headphones. There is a dedicated analogue mixer for OUT3 and one for
OUT4 as shown in Figure 31.
The OUT3 and OUT4 output stages are powered from SPKVDD and SPKGND. The individually
controllable outputs also incorporate an optional 1.5x boost and level shifting stage.
Figure 31 OUT3 and OUT4 Mixers



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