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WM8980CGEFL/V 데이터시트(PDF) 81 Page - Wolfson Microelectronics plc

부품명 WM8980CGEFL/V
상세설명  Stereo CODEC with Speaker Driver and Video Buffer
PDF  123 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8980CGEFL/V 데이터시트(HTML) 81 Page - Wolfson Microelectronics plc

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Pre-Production
WM8980
w
PP, Rev 3.8, May 2012
81
The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings
are shown in Table 60.
MCLK
(MHZ)
(F1)
DESIRED
OUTPUT
(MHZ)
F2
(MHZ)
PRESCALE
DIVIDE
POSTSCALE
DIVIDE
R
N
(HEX)
K
(HEX)
12
11.29
90.3168
1
2
7.5264
7
86C226
12
12.288
98.304
1
2
8.192
8
3126E8
13
11.29
90.3168
1
2
6.947446
6
F28BD4
13
12.288
98.304
1
2
7.561846
7
8FD525
14.4
11.29
90.3168
1
2
6.272
6
45A1CA
14.4
12.288
98.304
1
2
6.826667
6
D3A06E
19.2
11.29
90.3168
2
2
9.408
9
6872AF
19.2
12.288
98.304
2
2
10.24
A
3D70A3
19.68
11.29
90.3168
2
2
9.178537
9
2DB492
19.68
12.288
98.304
2
2
9.990243
9
FD809F
19.8
11.29
90.3168
2
2
9.122909
9
1F76F7
19.8
12.288
98.304
2
2
9.929697
9
EE009E
24
11.29
90.3168
2
2
7.5264
7
86C226
24
12.288
98.304
2
2
8.192
8
3126E8
26
11.29
90.3168
2
2
6.947446
6
F28BD4
26
12.288
98.304
2
2
7.561846
7
8FD525
27
11.29
90.3168
2
2
6.690133
6
BOAC93
27
12.288
98.304
2
2
7.281778
7
482296
Table 60 PLL Frequency Examples
LOOPBACK
Setting the LOOPBACK register bit enables digital loopback. When this bit is set the output data
from the ADC audio interface is fed directly into the DAC data input.
COMPANDING
The WM8980 supports A-law and
-law and companding and linear mode on both transmit (ADC)
and receive (DAC) sides. Companding can be enabled on the DAC or ADC audio interfaces by
writing the appropriate value to the DAC_COMP or ADC_COMP register bits respectively.



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