전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

CY8C56LP 데이터시트(PDF) 7 Page - Cypress Semiconductor

부품명 CY8C56LP
상세설명  Programmable System-on-Chip (PSoC짰)
PDF  120 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY8C56LP 데이터시트(HTML) 7 Page - Cypress Semiconductor

Back Button CY8C56LP Datasheet HTML 3Page - Cypress Semiconductor CY8C56LP Datasheet HTML 4Page - Cypress Semiconductor CY8C56LP Datasheet HTML 5Page - Cypress Semiconductor CY8C56LP Datasheet HTML 6Page - Cypress Semiconductor CY8C56LP Datasheet HTML 7Page - Cypress Semiconductor CY8C56LP Datasheet HTML 8Page - Cypress Semiconductor CY8C56LP Datasheet HTML 9Page - Cypress Semiconductor CY8C56LP Datasheet HTML 10Page - Cypress Semiconductor CY8C56LP Datasheet HTML 11Page - Cypress Semiconductor Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 120 page
background image
PRELIMINARY
PSoC® 5LP: CY8C56LP Family
Datasheet
Document Number: 001-84935 Rev. **
Page 7 of 120
Figure 2-4. 100-pin TQFP Part Pinout
Figure 2-5 and Figure 2-6 on page 8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 on page 8 and Power
System on page 24. The trace between the two VCCD pins should be as short as possible.
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
TQFP
(TRACEDATA[1] , GPIO)P2[5]
(TRACEDATA[2] , GPIO)P2[6]
(TRACEDATA[3] , GPIO)P2[7]
(I2C0 : SCL, SIO )P12[4]
(I2C0 : SDA, SIO )P12[5]
(GPIO)P6[4]
(GPIO)P6[5]
(GPIO)P6[6]
(GPIO)P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(GPIO)P5[0]
(GPIO)P5[1]
(GPIO)P5[2]
(GPIO)P5[3]
( TMS, SWDIO, GPIO)P1[0]
( TCK, SWDCK, GPIO)P1[1]
(Configurable XRES , GPIO)P1[2]
( TDO, SWV, GPIO)P1[3]
(TDI, GPIO)P1[4]
(NTRST, GPIO)P1[5]
VDDIO0
P0[3] ( GPIO,OPAMP0-/EXTREF0)
P0[2] ( GPIO, OPAMP 0+/SAR1 EXTREF)
P0[1] ( GPIO, OPAMP
0
OUT )
P0[0] ( GPIO, OPAMP
2
OUT )
P4[1] ( GPIO)
P4[0] ( GPIO)
P12[3] ( SIO)
P12[2] ( SIO)
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
P15[3] ( GPIO, KHZ XTAL:XI)
P15[2] ( GPIO, KHZ XTAL:XO)
P12[1] ( SIO,I2C1 : SDA)
P12[0] ( SIO,I2C1 : SCL)
P3[7] ( GPIO, OPAMP
3
OUT )
P3[6] ( GPIO, OPAMP
1
OUT )
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Lines show VDDIO
I/O Supply Association
Note
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com