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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F407IE 데이터시트(PDF) 128 Page - STMicroelectronics |
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STM32F407IE 데이터시트(HTML) 128 Page - STMicroelectronics |
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128 / 180 page  Electrical characteristics STM32F405xx, STM32F407xx 128/180 Doc ID 022152 Rev 3 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 50 or Figure 51, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 50. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. Figure 51. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176. VREF+ is also available on LQFP100, LQFP144, and LQFP176. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. V REF+ STM32F V DDA V SSA/V REF- 1 µF // 10 nF 1 µF // 10 nF ai17535 (See note 1) (See note 1) VREF+/VDDA STM32F 1 µF // 10 nF VREF–/VSSA ai17536 (See note 1) (See note 1) |
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