P13/29

Rev. M, May 2010

ML5012

1-4.

WR_SYS Command. Set AD conversion clock frequency, AD startup time, Successive AD conversion mode,

PGA Reference voltage to AGND or (VR-AGND)/2

The following diagram shows the timing diagram of writing data to control the AD conversion frequency.

The DIN data in C1~C4 cycle is WR_SYS command code.

The DIN data in C5~C7 cycles are output data of ADC Clock, D[11:9] = AD_Clock[2:0].

The DIN data in C8~C9 cycles are output data of Start time, D[8:7] = STA_OPT[1:0].

The DIN data in C10~C13 are reserved.

The DIN data in C14 is Successive AD mode enable, D[2] = SMODE.

The DIN data in C15 is Reference AGND connection enable, D[1] = VGND_EN.

The DIN data in C16 is Reference (VR-AGND)/2 connection enable, D[0] = VMID_EN.

Control

Function

D11

D10

D9

D8

D7

D2

D1

D0

Operations

0

0

0

AD Clock Frequency = 1MHz

0

0

1

AD Clock Frequency = 500kHz (default)

0

1

0

AD Clock Frequency = 250kHz

0

1

1

AD Clock Frequency = 125kHz

1

0

0

AD Clock Frequency = 62.5kHz

1

0

1

AD Clock Frequency = 31.25kHz

1

1

0

AD Clock Frequency = 15.625kHz

Set AD Clock Frequency

(AD_Clock[2:0])

1

1

1

AD Clock Frequency = 7.8125kHz

0

0

Startup Time = 1000us (default)

0

1

Startup Time = 800us

1

0

Startup Time = 600us

Set AD Converter Startup Time

(STA_OPT[1:0])

1

1

Startup Time = 400us

0

Successive AD conversion mode disable

Set Successive AD Conversion

Mode (SMODE)

1

Successive AD conversion mode enable

0

PGA Reference connect to AGND

Enable PGA reference connect to

VMIN (VMIN_EN)

1

PGA Reference connect to VMIN

-

Reserved

-