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ML5012 데이터시트(PDF) 16 Page - Minilogic Device Corporation Limited |
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ML5012 데이터시트(HTML) 16 Page - Minilogic Device Corporation Limited |
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16 / 29 page ![]() P16/29 Rev. M, May 2010 ML5012 1-7 RR_AD Command. Read data from A/D Register. The following diagram shows the timing diagram of read data from A/D Register. The DIN data in C1~C4 cycle is RR_AD command code. The DOUT data in C5~C16 cycles are output data from A/D Register, D[11:0] = A/D[11:0]. 1-8 RR_SYS Command. Read data from SYS Register. The following diagram shows the timing diagram of read data from A/D Register. The DIN data in C1~C4 cycle is RR_SYS command code. The DOUT data in C5~C7 cycles are output data of ADC Clock, D[11:9] = AD_Clock[2:0]. The DOUT data in C8~C9 cycles are output data of Start time, D[8:7] = STA_OPT[1:0]. The DOUT data in C10~C13 are reserved. The DOUT data in C14 is Successive AD mode enable, D[2] = SMODE. The DOUT data in C15 is Reference AGND connection enable, D[1] = VGND_EN. The DOUT data in C16 is Reference (VR-AGND)/2 connection enable, D[0] = VMID_EN. |
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