WM8782

Production Data

w

PD, April 2010, Rev 4.7

8

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

Figure 1 System Clock Timing Requirements

Test Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

11

ns

MCLK System clock pulse width low

11

ns

MCLK System clock cycle time

28

ns

MCLK duty cycle

40:60

60:40

Table 1 Master Clock Timing Requirements

AUDIO INTERFACE TIMING – MASTER MODE

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

0

10

ns

DOUT propagation delay from BCLK falling edge

0

10

ns

Table 2 Digital Audio Data Timing – Master Mode