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WM8782SEDS/V 데이터시트(PDF) 9 Page - Wolfson Microelectronics plc

부품명 WM8782SEDS/V
상세설명  24-Bit, 192kHz Stereo ADC
PDF  20 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8782SEDS/V 데이터시트(HTML) 9 Page - Wolfson Microelectronics plc

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Production Data
WM8782
w
PD, April 2010, Rev 4.7
9
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
DVDD = 3.3V, DGND = 0V, TA = +25
oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
LRCLK set-up time to BCLK rising edge
tLRSU
10
ns
LRCLK hold time from BCLK rising edge
tLRH
10
ns
DOUT propagation delay from BCLK falling edge
tDD
0
10
ns
Table 3 Digital Audio Data Timing – Slave Mode
Note:
LRCLK should be synchronous with MCLK.



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