WM8782

Production Data

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PD, April 2010, Rev 4.7

14

MASTER CLOCK AND AUDIO SAMPLE RATES

In a typical digital audio system there is only one central clock source producing a reference clock to

which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock (MCLK). The external master system clock can be applied directly through the MCLK

input pin. In a system where there are a number of possible sources for the reference clock it is

recommended that the clock source with the lowest jitter be used to optimise the performance of the

ADC.

The master clock is used to operate the digital filters and the noise shaping circuits. The WM8782

supports master clocks of 128fs, 192fs, 256fs, 384fs, 512fs and 768fs, where fs is the audio sampling

frequency (LRCLK). In Slave Mode, the WM8782 automatically detects the audio sample rate. In

Master Mode, LRCLK is generated for rate 256fs, unless the user changes this to 128fs using the

FSAMPEN pin = z (see Table 9 below). BCLK is also generated in Master Mode. BCLK=MCLK/4 for

256fs, and BCLK=MCLK/2 for 128fs.

Table 8 shows the common MCLK frequencies for different sample rates.

SAMPLING RATE

(LRCLK)

Master Clock Frequency (MHz)

128fs

192fs

256fs

384fs

512fs

768fs

8kHz

1.024

1.536

2.048

3.072

4.096

6.144

16kHz

2.048

3.072

4.096

6.144

8.192

12.288

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.144

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

-

-

192kHz

24.576

36.864

-

-

-

-

Table 8 Master Clock Frequency Selection

In Slave mode, the WM8782 has a master detection circuit that automatically determines the

relationship between the master clock frequency and the sampling rate (to within +/- 32 system

clocks). If there is a greater than 32 clocks error the interface sets itself to the highest rate available

(768fs). There must be a fixed number of MCLKS per LRCLK, although the WM8782 is tolerant of

phase variations or jitter on these clocks.

FSAMPEN

The FSAMPEN pin controls the over sampling rate of the ADC. The WM8782 can operate at sample

rates from 8kHz to 192kHz. The WM8782 uses a sigma-delta modulator that operates at an optimal

frequency of 6.144MHz.

By default the WM8782 generates the ADC frequency at 128xOSR. At fs=48kHz, the ADC frequency

is 128xOSR = 128x48kHz = 6.144MHz.

If fs=96KHz, the FSAMPEN pin must be set to 1. In this case, the ADC frequency is 64xOSR =

64x96kHz = 6.144MHz.

If fs=192KHz, the FSAMPEN pin must be set to z. In this case, the ADC frequency is 32xOSR =

32x192kHz = 6.144MHz.

It is recommended that the above settings are used for both master and slave mode.

PIN

DESCRIPTION

M/S

Master/Slave Selection

0 = Slave Mode (128fs, 192fs,

256fs, 384fs, 512fs, 768fs)

1= Master Mode (256fs, 128fs

when FSAMPEN=z)

FSAMPEN

Fast sampling rate enable

0 = 48ken (128x OSR)

1= 96ken (64x OSR)

z= 192ken (32x OSR)

Table 9 Master/Slave and Sampling Rate Enable Selection