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WM8782SEDS/V 데이터시트(PDF) 16 Page - Wolfson Microelectronics plc

부품명 WM8782SEDS/V
상세설명  24-Bit, 192kHz Stereo ADC
PDF  20 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8782SEDS/V 데이터시트(HTML) 16 Page - Wolfson Microelectronics plc

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WM8782
Production Data
w
PD, April 2010, Rev 4.7
16
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = DGND = 0V, TA = +25°C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power Supply Input Timing Information
DVDD level to activate POR –
power on
Vpora
Measured from DGND
0.7
V
AVDD level to activate POR –
power on
Vpora
Measured from AGND
0.7
V
VMID level to activate POR –
power on
Vpora
Measured from AGND
0.7
V
DVDD level to release POR –
power on (see notes 1 and 2)
Vporr
Measured from DGND
DVDD Min
V
AVDD level to release POR –
power on (see notes 1 and 2)
Vporr
Measured from AGND
AVDD Min
V
VMID level to release POR –
power on (see notes 1 and 2)
Vporr
Measured from AGND
1
V
POR active period (see notes
1 and 2)
tpor
Measured from POR
active to POR release
30
(note 6)
Defined by DVDD/AVDD/
VMID Rise Time
s
DVDD level to activate POR –
power off (see note 5)
Vpor_off
Measured from DGND
0.8
V
AVDD level to activate POR –
power off (see note 5)
Vpor_off
Measured from AGND
0.8
V
VMID level to activate POR –
power off (see note 5)
Vpor_off
Measured from AGND
0.7
V
Power on – POR propagation
delay through device
tpon
Measured from rising
EDGE of POR
30
s
Power down – POR
propagation delay through
device
tpoff
Measured from falling
EDGE of POR
30
s
Notes:
1.
POR is activated when DVDD or AVDD or VMID reach their stated Vpora level (Figure 11)
2.
POR is only released when DVDD and AVDD and VMID have all reached their stated Vporr levels (Figure 11).
3.
The rate of rise of VMID depends on the rate of rise of AVDD, the internal 50kΩ resistance and the external decoupling
capacitor. Typical tolerance of 50K resistor can be taken as +/-20%.
4.
If AVDD, DVDD or VMID suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go
below Vpor_off,), then the chip will not reset and will resume normal operation when the voltage is back to the
recommended level again.
5.
The chip will enter reset at power down when AVDD or DVDD or VMID falls below Vpor_off. This may be important if the
supply is turned on and off frequently by a power management system.
6.
The minimum tpor period is maintained even if DVDD, AVDD and VMID have zero rise time. This specification is
guaranteed by design rather than test.



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