ADP5050ACPZ-R7 datasheet(44/60 Pages) AD

부품명	ADP5050ACPZ-R7

상세설명	5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator

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44 / 60 page

ADP5050

Data Sheet

Rev. 0 | Page 44 of 60

Register 5 is used to configure dynamic voltage scaling (DVS) for Channel 1 and Channel 4 (see the Dynamic Voltage Scaling (DVS) section).

Table 27. Register 5 Bit Assignments

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

DVS4_ON

DVS4_INTVAL[1:0]

Reserved

DVS1_ON

DVS1_INTVAL[1:0]

Table 28. DVS_CFG Register, Bit Function Descriptions

Bits

Bit Name

Access

Description

Reserved

R/W

Reserved.

DVS4_ON

R/W

0 = disable DVS for Channel 4 (default).

1 = enable DVS for Channel 4.

[5:4]

DVS4_INTVAL[1:0]

R/W

These bits configure the DVS interval for Channel 4.

00 = 62.5 µs (default).

01 = 31.2 µs.

10 = 15.6 µs.

11 = 7.8 µs.

Reserved

R/W

Reserved.

DVS1_ON

R/W

0 = disable DVS for Channel 1 (default).

1 = enable DVS for Channel 1.

[1:0]

DVS1_INTVAL[1:0]

R/W

These bits configure the DVS interval for Channel 1.

00 = 62.5 µs (default).

01 = 31.2 µs.

10 = 15.6 µs.

11 = 7.8 µs.

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