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PIC24FV32KA302-I/ML 데이터시트(PDF) 60 Page - Microchip Technology

부품명 PIC24FV32KA302-I/ML
상세설명  20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology
PDF  364 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC24FV32KA302-I/ML 데이터시트(HTML) 60 Page - Microchip Technology

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PIC24FV32KA304 FAMILY
DS39995D-page 60
 2011-2013 Microchip Technology Inc.
5.5.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
The user can program one row of Flash program
memory at a time by erasing the programmable row.
The general process is as follows:
1.
Read a row of program memory (32 instructions)
and store in data RAM.
2.
Update the program data in RAM with the
desired new data.
3.
Erase a row (see Example 5-1):
a)
Set the NVMOPx bits (NVMCON<5:0>) to
‘011000’ to configure for row erase. Set the
ERASE
(NVMCON<6>)
and
WREN
(NVMCON<14>) bits.
b)
Write the starting address of the block to be
erased into the TBLPAG and W registers.
c)
Write 55h to NVMKEY.
d)
Write AAh to NVMKEY.
e)
Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the
duration of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
4.
Write the first 32 instructions from data RAM into
the program memory buffers (see Example 5-1).
5.
Write the program block to Flash memory:
a) Set the NVMOPx bits to ‘011000’ to
configure for row programming. Clear the
ERASE bit and set the WREN bit.
b) Write 55h to NVMKEY.
c)
Write AAh to NVMKEY.
d)
Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash
memory is done, the WR bit is cleared
automatically.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
must wait for the programming time until programming
is complete. The two instructions following the start of
the programming sequence should be NOPs, as shown
in Example 5-5.
EXAMPLE 5-1:
ERASING A PROGRAM MEMORY ROW – ASSEMBLY LANGUAGE CODE
; Set up NVMCON for row erase operation
MOV
#0x4058, W0
;
MOV
W0, NVMCON
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
#tblpage(PROG_ADDR), W0
;
MOV
W0, TBLPAG
; Initialize PM Page Boundary SFR
MOV
#tbloffset(PROG_ADDR), W0
; Initialize in-page EA[15:0] pointer
TBLWTL W0, [W0]
; Set base address of erase block
DISI
#5
; Block all interrupts
for next 5 instructions
MOV
#0x55, W0
MOV
W0, NVMKEY
; Write the 55 key
MOV
#0xAA, W1
;
MOV
W1, NVMKEY
; Write the AA key
BSET
NVMCON, #WR
; Start the erase sequence
NOP
; Insert two NOPs after the erase
NOP
; command is asserted



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