PIC16F883-ESLASHSO. datasheet(202/338 Pages) MICROCHIP

202 / 338 page

PIC16F882/883/884/886/887

DS41291G-page 202

 2006-2012 Microchip Technology Inc.

13.4.8

I2C™ MASTER MODE

TRANSMISSION

Transmission of a data byte, a 7-bit address, or the

other half of a 10-bit address, is accomplished by sim-

ply writing a value to the SSPBUF register. This action

will set the Buffer Full bit, BF, and allow the Baud Rate

Generator to begin counting and start the next trans-

mission. Each bit of address/data will be shifted out

onto the SDA pin after the falling edge of SCL is

asserted (see data hold time specification, parameter

106). SCL is held low for one Baud Rate Generator roll-

over count (TBRG). Data should be valid before SCL is

released high (see data setup time specification,

parameter 107). When the SCL pin is released high, it

is held that way for TBRG. The data on the SDA pin

must remain stable for that duration and some hold

time after the next falling edge of SCL. After the eighth

bit is shifted out (the falling edge of the eighth clock),

the BF bit is cleared and the master releases SDA,

allowing the slave device being addressed to respond

with an ACK bit during the ninth bit time, if an address

match occurs, or if data was received properly. The

status of ACK is written into the ACKDT bit on the fall-

ing edge of the ninth clock. If the master receives an

Acknowledge, the Acknowledge Status bit, ACKSTAT,

is cleared. If not, the bit is set. After the ninth clock, the

SSPIF bit is set and the master clock (Baud Rate Gen-

erator) is suspended until the next data byte is loaded

into the SSPBUF, leaving SCL low and SDA

unchanged (Figure 13-15).

After the write to the SSPBUF, each bit of the address

will be shifted out on the falling edge of SCL, until all

seven address bits and the R/W bit, are completed. On

the falling edge of the eighth clock, the master will de-

assert the SDA pin, allowing the slave to respond with

an Acknowledge. On the falling edge of the ninth clock,

the master will sample the SDA pin to see if the address

was recognized by a slave. The status of the ACK bit is

loaded into the ACKSTAT Status bit (SSPCON2 regis-

ter). Following the falling edge of the ninth clock trans-

mission of the address, the SSPIF is set, the BF bit is

cleared and the Baud Rate Generator is turned off, until

another write to the SSPBUF takes place, holding SCL

low and allowing SDA to float.

13.4.8.1

BF Status Flag

In Transmit mode, the BF bit (SSPSTAT register) is set

when the CPU writes to SSPBUF, and is cleared when

all eight bits are shifted out.

13.4.8.2

WCOL Status Flag

If the user writes the SSPBUF when a transmit is

already in progress (i.e., SSPSR is still shifting out a

data byte), the WCOL is set and the contents of the buf-

fer are unchanged (the write doesn’t occur). WCOL

must be cleared in software.

13.4.8.3

ACKSTAT Status Flag

In Transmit mode, the ACKSTAT bit (SSPCON2

Acknowledge (ACK = 0), and is set when the slave

does not Acknowledge (ACK = 1). A slave sends an

Acknowledge when it has recognized its address

(including a general call), or when the slave has

properly received its data.

13.4.9

I2C™ MASTER MODE RECEPTION

Master mode reception is enabled by programming the

Receive Enable bit, RCEN (SSPCON2 register).

The Baud Rate Generator begins counting, and on

each rollover, the state of the SCL pin changes (high-

to-low/low-to-high) and data is shifted into the SSPSR.

After the falling edge of the eighth clock, the RCEN bit

is automatically cleared, the contents of the SSPSR are

loaded into the SSPBUF, the BF bit is set, the SSPIF

flag bit is set and the Baud Rate Generator is sus-

pended from counting, holding SCL low. The MSSP is

now in Idle state, awaiting the next command. When

the buffer is read by the CPU, the BF bit is automati-

cally cleared. The user can then send an Acknowledge

bit at the end of reception, by setting the Acknowledge

Sequence Enable bit ACKEN (SSPCON2 register).

13.4.9.1

BF Status Flag

In receive operation, the BF bit is set when an address

or data byte is loaded into SSPBUF from SSPSR. It is

cleared when the SSPBUF register is read.

13.4.9.2

SSPOV Status Flag

In receive operation, the SSPOV bit is set when eight

bits are received into the SSPSR and the BF bit is

already set from a previous reception.

13.4.9.3

WCOL Status Flag

If the user writes the SSPBUF when a receive is

already in progress (i.e., SSPSR is still shifting in a data

byte), the WCOL bit is set and the contents of the buffer

are unchanged (the write doesn’t occur).

Note:

The MSSP module must be in an Idle state

before the RCEN bit is set, or the RCEN bit

will be disregarded.

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