PIC16F883-ESLASHSO. datasheet(207/338 Pages) MICROCHIP

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 2006-2012 Microchip Technology Inc.

DS41291G-page 207

PIC16F882/883/884/886/887

13.4.15

MULTI-MASTER MODE

In Multi-Master mode, the interrupt generation on the

detection of the Start and Stop conditions allows the

determination of when the bus is free. The Stop (P) and

Start (S) bits are cleared from a Reset, or when the

MSSP module is disabled. Control of the I2C bus may

be taken when the P bit (SSPSTAT register) is set, or

the bus is idle with both the S and P bits clear. When

the bus is busy, enabling the SSP Interrupt will gener-

ate the interrupt when the Stop condition occurs.

In Multi-Master operation, the SDA line must be moni-

tored for arbitration, to see if the signal level is the

expected output level. This check is performed in hard-

ware, with the result placed in the BCLIF bit.

Arbitration can be lost in the following states:

• Address transfer

• Data transfer

• A Start condition

• A Repeated Start condition

• An Acknowledge condition

13.4.16

MULTI -MASTER

COMMUNICATION, BUS

COLLISION, AND BUS

ARBITRATION

Multi-Master mode support is achieved by bus arbitra-

tion. When the master outputs address/data bits onto

the SDA pin, arbitration takes place when the master

outputs a ‘1’ on SDA, by letting SDA float high and

another master asserts a ‘0’. When the SCL pin floats

high, data should be stable. If the expected data on

SDA is a ‘1’ and the data sampled on the SDA pin = 0,

then a bus collision has taken place. The master will set

the Bus Collision Interrupt Flag (BCLIF) and reset the

I2C port to its Idle state (Figure 13-20).

If a transmit was in progress when the bus collision

occurred, the transmission is halted, the BF bit is

cleared, the SDA and SCL lines are de-asserted, and

the SSPBUF can be written to. When the user services

the bus collision interrupt service routine, and if the I2C

bus is free, the user can resume communication by

asserting a Start condition.

If a Start, Repeated Start, Stop, or Acknowledge

condition was in progress when the bus collision

occurred, the condition is aborted, the SDA and SCL

lines are de-asserted, and the respective control bits in

the SSPCON2 register are cleared. When the user

services the bus collision interrupt service routine, and

if the I2C bus is free, the user can resume

communication by asserting a Start condition.

The master will continue to monitor the SDA and SCL

pins. If a Stop condition occurs, the SSPIF bit will be

set.

A write to the SSPBUF will start the transmission of

data at the first data bit, regardless of where the trans-

mitter left off when the bus collision occurred.

In Multi-Master mode, the interrupt generation on the

detection of Start and Stop conditions allows the

determination of when the bus is free. Control of the I2C

bus can be taken when the P bit is set in the SSPSTAT

cleared.

FIGURE 13-20:

BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE

SDA

SCL

BCLIF

SDA released

SDA line pulled low

by another source

Sample SDA,

While SCL is high, data doesn’t

Bus collision has occurred

Set bus collision

interrupt (BCLIF)

match what is driven by the master,

by master

Data changes

while SCL = 0

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