PIC16F883-ESLASHSO. datasheet(273/338 Pages) MICROCHIP

273 / 338 page

 2006-2012 Microchip Technology Inc.

DS41291G-page 273

PIC16F882/883/884/886/887

TABLE 17-14: SPI MODE REQUIREMENTS

FIGURE 17-18:

I2C™ BUS START/STOP BITS TIMING

Param

No.

Symbol

Characteristic

Min.

Typ† Max. Units Conditions

70*

TSSL2SCH,

TSSL2SCL

 to SCK or SCK input

TCY

——

71*

TSCH

SCK input high time (Slave mode)

TCY + 20

—

72*

TSCL

SCK input low time (Slave mode)

TCY + 20

—

73*

TDIV2SCH,

TDIV2SCL

Setup time of SDI data input to SCK edge

100

—

74*

TSCH2DIL,

TSCL2DIL

Hold time of SDI data input to SCK edge

100

—

75*

TDOR

SDO data output rise time

3.0-5.5V

—

2.0-5.5V

—

76*

TDOF

SDO data output fall time

—

77*

TSSH2DOZSS

 to SDO output high-impedance

—

78*

TSCR

SCK output rise time

(Master mode)

3.0-5.5V

—

2.0-5.5V

—

79*

TSCF

SCK output fall time (Master mode)

—

80*

TSCH2DOV,

TSCL2DOV

SDO data output valid after

SCK edge

3.0-5.5V

—

2.0-5.5V

—

145

81*

TDOV2SCH,

TDOV2SCL

SDO data output setup to SCK edge

Tcy

—

82*

TSSL2DOV

SDO data output valid after SS

 edge

—

83*

TSCH2SSH,

TSCL2SSH

after SCK edge

1.5TCY + 40

—

* These parameters are characterized but not tested.

† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note: Refer to Figure 17-3 for load conditions.

SCL

SDA

Start

Condition

Stop

Condition

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